[1]A. BONFANTI, S. LEVANTINO, S. PELLERANO, C. SAMORI, A. L. LACAITA, and F. TORRISI. A voltage-controlled oscillator for ieee 802.11a and hiperlan2 application. In Proceedings of the 29th European Solid-State Circuits Conference, 2003. ESSCIRC 2003, pages 695–698, 16-18 Sept. 2003.

[2]A. BONFANTI, S. LEVANTINO, L. ROMANO’, C. SAMORI, and A. L. LACAITA. A varactor configuration minimizing flicker noise up-conversion in vcos. In Proceedings of IEEE 2004 Workshop on Wireless Circuits and Systems. WoWCAS 2004, pages 25–26, 21-22 May 2004.

[3]A. BONFANTI, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. A varactor configuration minimizing the amplitude-to-phase noise conversion in vcos. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, 53:481–488, 2006.

[4]S. GIERKINK, V. BOCCUZZI, R. FRYE, and S. LEVANTINO. Patent number us2003000631531: Us20040066241a1: Quadrature voltage controlled oscillator utilizing common-mode inductive coupling, 2003.

[5]S. GIERKINK, S. LEVANTINO, R. FRYE, C. SAMORI, and V. BOCCUZZI. A low-phase-noise 5-ghz cmos quadrature vco using superharmonic coupling. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 38:1148–1154, 2003.

[6]S. J. L. GIERKINK, S. LEVANTINO, R. C. FRYE, and V. BOCCUZZI. A low-phase-noise 5ghz quadrature cmos vco using common-mode inductive coupling. In Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002, pages 539–542, 24-26 Sept. 2002.

[7]S. L. J. GIERKINK and S. LEVANTINO. Patent number us2003000628162: Us20040127172a1: Phase-error suppressor and a method of suppressing phase-error, 2003.

[8]A. L. LACAITA, S. LEVANTINO, and C. SAMORI. Integrated Frequency Synthesizers for Wireless Systems. Cambridge University Press, Cambridge, UK, 2007.

[9]S. LEVANTINO, A. BONFANTI, L. ROMANO’, C. SAMORI, and A. L. LACAITA. A 2-ghz differentially-tuned vco with reduced flicker noise up-conversion. In Proceedings of the 21st IEEE Norchip Conference 2003. NORCHIP 2003, pages 163–166, 10-11 Nov. 2003.

[10]S. LEVANTINO, A. BONFANTI, L. ROMANO’, C. SAMORI, and A. L. LACAITA. Differential tuning oscillators with reduced flicker noise upconversion. In Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004, pages 33–36, 13-15 Dec. 2004.

[11]S. LEVANTINO, A. BONFANTI, L. ROMANÒ, C. SAMORI, and A. L. LACAITA. Differentially-tuned vco with reduced tuning sensitivity and flicker noise up-conversion. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 42:21–29, 2005.

[12]S. LEVANTINO, L. COLLAMATI, C. SAMORI, and A. L. LACAITA. Folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, 57:671–675, 2010.

[13]S. LEVANTINO, M. MILANI, C. SAMORI, and A. L. LACAITA. Fast-switching analog pll with finite-impulse response. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, 51:1697–1701, 2004.

[14]S. LEVANTINO, L. ROMANO’, S. PELLERANO, C. SAMORI, and A. L. LACAITA. Phase noise in digital frequency dividers. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 39:775–784, 2004.

[15]S. LEVANTINO, L. ROMANO’, C. SAMORI, and A. L. LACAITA. Fast-switching analog pll with finite-impulse response. In Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS ’04, volume 4, pages IV–165–IV–168, 23-26 May 2004.

[16]S. LEVANTINO, C. SAMORI, M. BANU, V. BOCCUZZI, and J. GLAS. A cmos if sampling circuit with reduced aliasing for wireless applications. In Digest of Technical Papers of IEEE International Solid-State Circuits Conference, 2002. ISSCC 2002, volume 1, pages 404–405, 3-7 Feb. 2002.

[17]S. LEVANTINO, C. SAMORI, M. BANU, J. GLAS, and V. BOCCUZZI. A cmos gsm if-sampling circuit with reduced in-channel aliasing. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 38:895–904, 2003.

[18]S. LEVANTINO, C. SAMORI, A. BONFANTI, S. L. J. GIERKINK, A. L. LACAITA, and V. BOCCUZZI. Frequency dependence on bias current in 5 ghz cmos vcos: impact on tuning range and flicker noise upconversion. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37:1003–1011, 2002.

[19]S. LEVANTINO, C. SAMORI, A. ZANCHI, and A. L. LACAITA. Am-to-pm conversion in varactor-tuned oscillators. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, 49:509–513, 2002.

[20]S. LEVANTINO, X. WANG, C. SAMORI, P. ANDREANI, and A. LACAITA. A circuit technique improving the image rejection of rf front-ends. In Digest of Technical Papers of 2004 Symposium on VLSI Circuits, pages 368–371, 17-19 June 2004.

[21]S. LEVANTINO, A. ZANCHI, A. BONFANTI, and C. SAMORI. Fast simulation techniques for phase noise analysis of oscillators. In Proceedings of the IEEE International Symposium on Circuits And Systems, 2000. ISCAS 2000, volume 2, pages II–156–II–159, 28-31 May 2000.

[22]S. LEVANTINO, M. ZANUSO, P. MADOGLIO, D. TASCA, C. SAMORI, and A. L. LACAITA. Ad-pll for wimax with digitally-regulated tdc and glitch correction logic. EURASIP JOURNAL ON EMBEDDED SYSTEMS, 2010:1–8, 2010.

[23]S. LEVANTINO, M. ZANUSO, and C. SAMORI. Patent number mi2009a000077: Convertitore tempo-digitale e sistema elettronico impiegante il convertitore, 2009.

[24]S. LEVANTINO, M. ZANUSO, and C. SAMORI. Patent number mi2009a000125: Oscillatore elettronico con ridotto rumore di fase, 2009.

[25]S. LEVANTINO, M. ZANUSO, and C. SAMORI. Patent number pct/ep2010/050440: A time-digital converter and an electronic system implementing the converter, 2010.

[26]S. LEVANTINO, M. ZANUSO, C. SAMORI, and A. L. LACAITA. Suppression of flicker noise upconversion in a 65nm cmos vco in the 3.0-to-3.6ghz band. In Digest of Technical Papers of the 2010 IEEE International Solid-State Circuits Conference. ISSCC 2010, pages 50–51, 7-11 February 2010.

[27]S. LEVANTINO, M. ZANUSO, D. TASCA, C. SAMORI, and A. L. LACAITA. An all-digital architecture for low-jitter regulated delay lines. In Proceedings of IEEE International Conference on Electronics, Circuits and Systems 2009. ICECS 2009, pages 603–606, 13-16 December 2009.

[28]P. MADOGLIO, M. ZANUSO, S. LEVANTINO, C. SAMORI, and A. LACAITA. Quantization effects in all-digital phase-locked loops. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, 54:1120–1124, 2007.

[29]G. MARZIN, L. COLLAMATI, S. LEVANTINO, and C. SAMORI. Folding of phase spectrum in phase-locked loops. In IEEJ International Analog VLSI Workshop. 13th Edition. AVLSIWS 2010, pages 231–236, 8-10 September 2010.

[30]L. PANSERI, L. ROMANO’, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. Low-power all-analog component separator for an 802.11a/g linc transmitter. In Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006. Solid-State Circuits Conference, 2006. ESSCIRC 2006., pages 271–274, 19-21 Sept. 2006.

[31]L. PANSERI, L. ROMANO’, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. Low-power cmos ieee 802.11a/g signal separator for outphasing transmitter. In IEEE Custom Integrated Circuits Conference 2006, pages 133–136, 10-13 Sept. 2006.

[32]L. PANSERI, L. ROMANÒ, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. Low-power signal component separator for a 64-qam 802.11 linc transmitter. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 43:1274–1286, 2008.

[33]S. PELLERANO, S. LEVANTINO, C. SAMORI, and A. LACAITA. A dual-band frequency synthesizer for 802.11a/b/g with fractional-spur averaging technique. In Digest of Technical Papers of IEEE International Solid-State Circuits Conference, 2005. ISSCC 2005., volume 1, pages 104–105, 10-14 Feb. 2005.

[34]S. PELLERANO, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. A 2-ghz low-power low-noise cmos 32/33 prescaler. In Proceedings of the 21st IEEE Norchip Conference 2003. NORCHIP 2003, pages 256–259, USA, 10-11 Nov. 2003.

[35]S. PELLERANO, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. A 13.5-mw 5-ghz frequency synthesizer with dynamic logic frequency divider. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 39:378–383, 2004.

[36]S. PELLERANO, C. SAMORI, S. LEVANTINO, and A. L. LACAITA. 13.5-mw, 5-ghz wlan, cmos frequency synthesizer using a true single phase clock divider. In Digest of Technical Papers of 2003 Symposium on VLSI Circuits, pages 145–158, 12-14 June 2003.

[37]L. ROMANO’, A. BONFANTI, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. 5-ghz oscillator array with reduced flicker up-conversion in 0.13-um cmos. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 41:2457–2467, 2006.

[38]L. ROMANO’, S. LEVANTINO, A. BONFANTI, C. SAMORI, and A. L. LACAITA. Phase noise and accuracy in quadrature oscillators. In Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS ’04, volume 1, pages I–161–I–164, 23-26 May 2004.

[39]L. ROMANO’, S. LEVANTINO, S. PELLERANO, C. SAMORI, and A. LACAITA. Low jitter design of a 0.35-um-cmos frequency divider operating up to 3 ghz. In Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002, pages 611–614, 24-26 Sept. 2002.

[40]L. ROMANO’, S. LEVANTINO, C. SAMORI, and A. LACAITA. Multiphase lc oscillators. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, 53:1579–1588, 2006.

[41]L. ROMANO’, C. SAMORI, S. LEVANTINO, A. BONFANTI, and A. L. LACAITA. A multi-tank lc-oscillator. In Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004, pages 29–32, 13-15 Dec. 2004.

[42]C. SAMORI, A. L. LACAITA, A. ZANCHI, S. LEVANTINO, and G. CALI’. Phase noise degradation at high oscillation amplitudes in lc-tuned vco’s. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 35:96–99, 2000.

[43]C. SAMORI, A. L. LACAITA, A. ZANCHI, S. LEVANTINO, and F. TORRISI. Impact of indirect stability on phase noise performance of fully–integrated lc tuned vcos. In Proceedings of the 25th European Solid-State Circuits Conference, pages 202–205, 21-23 Sept. 1999.

[44]C. SAMORI, S. LEVANTINO, and V. BOCCUZZI. A -94 dbc/hz@100 khz, fully-integrated, 5-ghz, cmos vco with 18 tuning range for bluetooth applications. In Proceedings of IEEE Conference on Custom Integrated Circuits, 2001. CICC 2001, pages 201–204, 6-9 May 2001.

[45]C. SAMORI, S. LEVANTINO, and A. L. LACAITA. Integrated lc oscillators for frequency synthesis in wireless applications. IEEE COMMUNICATIONS MAGAZINE, 40:166–171, 2002.

[46]C. SAMORI, A. ZANCHI, S. LEVANTINO, and A. L. LACAITA. A fully-integrated low-power low-noise 2.6-ghz bipolar vco for wireless applications. IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 11:199–201, 2001.

[47]D. TASCA, M. ZANUSO, S. LEVANTINO, and C. SAMORI. An automatic retiming system for asynchronous fractional frequency dividers. In 2010 Conference on Ph.D. Research in Microelectronics and Electronics. PRIME 2010, pages 1–4, 18-21 July 2010.

[48]A. ZANCHI, A. BONFANTI, S. LEVANTINO, and C. SAMORI. General sscr vs. cycle-to-cycle jitter relationship with application to the phase noise in pll. In Proceedings of Southwest Symposium on Mixed-Signal Design 2001. SSMSD 2001, pages 32–37, 25-27 Feb. 2001.

[49]A. ZANCHI, A. BONFANTI, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. Automatic amplitude control loop for a 2-v, 2.5-ghz lc-tank vco. In Proceedings of IEEE Custom Integrated Circuit Conference 2001. CICC 2001, pages 209–212, 6-9 May 2001.

[50]A. ZANCHI, C. SAMORI, A. L. LACAITA, and S. LEVANTINO. Impact of aac design on phase noise performance of vcos. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, 48:537–547, 2001.

[51]A. ZANCHI, C. SAMORI, S. LEVANTINO, and A. L. LACAITA. A 2-v 2.5-ghz-104-dbc/hz at 100khz fully integrated vco with wide-band low-noise automatic amplitude control loop. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 36:611–619, 2001.

[52]M. ZANUSO, S. LEVANTINO, and C. SAMORI. Patent number mi2009a000289: Dispositivo elettronico per generare una frequenza frazionaria, 2009.

[53]M. ZANUSO, S. LEVANTINO, and C. SAMORI. Patent number pct/ep2010/051265: Electronic device for generating a fractional frequency, 2010.

[54]M. ZANUSO, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. A 3mhz-bw 3.6ghz digital fractional-n pll with sub-gate-delay tdc, phase-interpolation divider, and digital mismatch cancellation. In Digest of Technical Papers of the 2010 IEEE International Solid-State Circuits Conference. ISSCC 2010, pages 476–477, 7-11 February 2010.

[55]M. ZANUSO, S. LEVANTINO, D. TASCA, D. RAITERI, C. SAMORI, and A. L. LACAITA. A glitch-corrector circuit for low-spur adplls. In Proceedings of IEEE International Conference on Electronics, Circuits and Systems 2009. ICECS 2009, pages 595–598, 13-16 December 2009.

[56]M. ZANUSO, P. MADOGLIO, S. LEVANTINO, C. SAMORI, and A. L. LACAITA. Time-to-digital converter for frequency synthesis based on a digital bang-bang dll. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, 57:548–555, 2010.

[57]M. ZANUSO, D. TASCA, S. LEVANTINO, A. DONADEL, C. SAMORI, and A. L. LACAITA. Noise analysis and minimization in bang-bang digital plls. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, 56:835–839, 2009.